Chip/SoC design & release
Composer is a tool that can be used by ASIC designers, even those who are focused on a complex SoC design, to greatly accelerate the integration and design process by eliminating many of the pain points in SoC design through automation.
Composer allows you to automate wire connections by encapsulating IPs into protocol based cable connections, which allows for quick connections between IPs, and quick creation of variant designs painlessly by the designer.
Composer also includes many tools to streamline your workflow such as generators and the ability to manage glue logic for connections between IPs. These tools can be used to accelerate the development of SoCs to deliver to market quickly.
|
Top down design for chips
Even the design teams that use top down design approach instead
of commonly used bottom up stitching approach can get the benefit as well.
Composer IDE supports and expedites both paradigms equally.
The top down approach can offer productivity and stability
for teams that demand to
work with a well proven mature long lasting established
architecture.
They produce number of chips with
incremental variations on features,
process technology and performance.
The chip architect usually puts together the the
hierarchical structures supporting the architecture.
The IPs are subsequently produced
with the required incremental changes, or even sometimes from scratch.
The IPs can be attached seamlessly as long as IPs comply with the
prebuilt structure.
Composer IDE helps you to put together the top down structure for your
chip or SoCs in a quick and efficient manner. It also helps to create the
necessary elements so that flavors of chips can be completed quickly.
|
IP design & delivery
IP reuse is central to the Composer IDE feature set.
Whether you are an IP vendor or an in-house IP provider,
you can increase the value of your existing IP by delivering
them in a way such that they can be quickly integrated in a chip.
You can also use Composer IDE to expedite any brand new IP designs.
At the end, faster the chip is built, quicker will be the return of investment. Reaching to success will be more than a step closer.
Scale with smart IP
In order to scale IPs such as network on chip (NoC),
bus bridges/switches, analog wrappers,
clock and power management across many chips, designers write script or software to produce the actual RTL modeled after a proven Verilog RTL. Composer IDE streamlines the process to make this software development simpler.
The IDE makes the integration equally simpler just like it does for the real RTL.
If you are an IP vendor or an in-house IP provider delivering IPs in form of script
or software, Composer IDE will take you a long way.
| 
