Home‎ > ‎

Adjust RTL hierarchy to meet your need

Hierarchical design allows grouping IPs together for various design reasons. The following are examples,
  • Reduce the number of long wires on silicon.
  • Reduce power consumption based on use case by grouping on a power island.
Connections between two IPs can extend across hierarchical boundaries. Changing the design may involve adding new IP or removing an existing IP which requires RTL changes in each level.

Hierarchy changes can happen during the design lifecycle as well. For instance, a change in power islands could mean big RTL changes in restructuring the hierarchy.

Let's say we are designing a chip called orion in Composer IDE that looks like the following. 



When we use Composer to build the RTL, the IDE will report the following hierarchy, 

    orion : {
        comm : {
            comm.gpio_ctl
            comm.uart_ctl
        }
        padring
        proc : {
            proc.intr
            proc.bridge
            proc.proc
        }
        storage : {
            storage.sram
            storage.dma
            storage.sdio_ctl
            storage.sram_ctl
            storage.sdram_ctl
        }
    }


Let's say we need to move the sdram controller, sdram_ctl to the top level due to newly imposed timing and power domain related requirements. If you are editing verilog this can be somewhat of a real headache. Imagine moving more blocks than just one.

In Composer IDE, this task is quite a bit of fun! All we need is the following few intutive SoCBuilder statements, 

    hierarchy auto {
        comm : {
            comm.gpio_ctl
            comm.uart_ctl
        }
        padring
        storage.sdram_ctl
        proc : {
            proc.intr
            proc.bridge
            proc.proc
        }
        storage : {
            storage.sram
            storage.dma
            storage.sdio_ctl
            storage.sram_ctl
        }
    }

Now the produced RTL will look like the following block diagram,



As you can see, the sdram controller has moved to the top level. It really is that simple. Move as many blocks as you like, create brand new levels, or collapse a few! Just mold the way a sculptor molds the clay to produce a shape that he really needs.

Your designers will be fully empowered beyond the limits of hierarchy. They can organize their design the way it makes sense to them using functional cohesion. Later, it can be morphed into the structure that works out for a given application. A common architecture can be reused over many chips, many silicon feature sizes, to serve many application domain requirements without worries. Easy reuse is the central theme of Composer IDE.

Composer IDE is packed with even more capabilities to improve chip design productivity. Contact us to arrange for a demo to go over the full capability of Composer IDE.