Chip/SoC Design

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Tangle of wires

In a chip or SoC, RTL designers have to connect many IPs. These connections comprise of many wires. Most of the times a group of functionally related wires are to be connected between two IPs. For instance the red colored lines in following Verilog code are related to connecting a group of functionally related wires between a bus bridge and an interrupt controller. In fact, you are well aware of the connections for widely used buses such as APB, AHB or AXI in your chip contain quite a large number of wires.

Verilog code

module proc ( input proc_proc_clk_clk, input bus_clk_proc_x0_clk, ... ... ); ... ... wire [7:0] bridge_proc1_bus_ipb_write_data; wire intr_system_bus_spb_active_n; wire intr_system_bus_spb_done; wire intr_system_bus_spb_write_en; wire [15:0] intr_system_bus_spb_address; wire [7:0] intr_system_bus_spb_read_data; wire [7:0] intr_system_bus_spb_write_data; interrupt1x8_controller intr ( .BUS_CLK(intr_bus_clk_clk), .RESET(intr_power_on_reset_rst), .ACK(intr_system_bus_spb_done), .ACTV_BAR(intr_system_bus_spb_active_n), .ADDR(intr_system_bus_spb_address[11:0]), .RD_DATA(intr_system_bus_spb_read_data[7:0]), .WEN(intr_system_bus_spb_write_en), .WRT_DATA(intr_system_bus_spb_write_data[7:0]), .ACK1(intr_interrupt1_ack), ... ... ); bridge2x4i8s bridge ( .BUS_CLK(bridge_bus_clk_clk), .RESET(bridge_power_on_reset_rst), .SPB_MASTER1_ACK(intr_system_bus_spb_done), .SPB_MASTER1_ACTV_BAR(intr_system_bus_spb_active_n), .SPB_MASTER1_ADDR(intr_system_bus_spb_address[11:0]), .SPB_MASTER1_RD_DATA(intr_system_bus_spb_read_data[7:0]), .SPB_MASTER1_WEN(intr_system_bus_spb_write_en), .SPB_MASTER1_WRT_DATA(intr_system_bus_spb_write_data[7:0]), .SPB_MASTER2_ACK(dma_system_bus_spb_done), ... ... ); ... ... endmodule //proc

Manually producing this Verilog can be tedious and error prone! Specially when there are lot of buses to connect in a chip.

There is a better way to hook up these large number of wires in Composer IDE that uses SoCBuilder language to generate the RTL. All the red colored Verilog code above can simply be produced by the following single line of SoCBuilder code.

Can your RTL designers make use of such a simple powerful scheme?

SoCBuilder code

connect bridge.spb1_bus and intr.system_bus;

This yields to an immediate boost in RTL productivity. Now it is possible to free up time for the designers to spend on the real design issues. Your organization does not have to be resource limited to bring quality in the chip design.

This is called a protocol based connection.

Chip/SoC Design

Tangle of wires

Verilog code

SoCBuilder code

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