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Composer Features

Composer is a Linux based IDE. The IDE is compiler technology driven.

  • Composer uses SoCBuilder, a simple intuitive language with quick learning curve. It typically takes one week to get up to speed to use the language for a chip project in a productive manner.
  • Using SoCBuilder directives, Composer generates all necessary RTL for IP integration in a chip. 
  • IDE checks syntax and semantic errors live as you type. Catch and prevent errors before they can cause productivity issues.
  • Promotes collaborative team friendly design environment.
  • Version control enabled. Subversion, git, CVS etc. Check in, check out, diff right within the IDE. 

Connect IPs fast and easy without errors.

  • Protocol based connection across hierarchy to reduce manual effort and common mistakes.

Change design hierarchy in a push button effort.

  • Retarget the design to change power domain.
  • Retarget to FPGA.

Perform quick feature change across multiple derivative designs based on same architecture.

Adding/deleting IP is minimal effort.

  • Layered connectivity without effecting RTL hierarchy.

Automated assertion binding to expedite DV.

  • Generates RTL binding of all the assertion files for IP and interface protocol verification at the appropriate level.

IP metadata encapsulation to improve reusability.

  • IP-XACT enabled.

Standardizes IPs to allow reuse across many chips.

  • IPs are standardized with protocol based connectivity.
  • IP uniquification enabled for legacy IPs.

Scale your silicon proven IPs by converting them to smart IPs.

  • Smart IP: Dynamic generation of chip specific IP using the proven IP as a template.

Streamline the RTL release customized just right for your organization.

Allows designing SoC, chip or IP with a significant improvement in frontend productivity.

  • Your design team will embrace market demand instead of resisting changes since the impact on schedule due to changes will be notably reduced.