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Design and standardize IPs for reuse

Connecting IPs in a chip or SoC could involve many wires. Connecting them could be tedious and error prone. However if we use protocol based connectivity to standardize the IP, we can make the task quite simple. It makes an IP readily reusable.

So, what really is a protocol based connection? >>

Think about a TV and DVD player. They are connected with a standard cable, since both the TV and DVD player has standard connection. Connecting them is only hooking your TV with DVD player with perhaps an HDMI cable. We will not need to worry about individual wires inside the cable. They will all get connected to the right place!

Box with cable connector paradigm

To standardize IPs, we will use the same idea as the TV and DVD player. We will need to do the equivalent of putting each of the IPs in their own boxes and affix connectors on the box. We need to connect these connectors with the ports of the IP inside the box. Once we complete these, we will have a box that can be connected with other boxes using an equivalent of the cables. It will prevent one from connecting master to master or connecting to the wrong kind of cable. The connector simply won't match. Just like in the real world you cannot connect VGA cable to an HDMI or you cannot connect male to male. This is an intuitive way to build a chip or SoC when you are dealing with lots of connections.

Let us examine how Composer IDE provides capability to accomplish this task. Let us say we have an interrupt controller IP with following ports,

Verilog Code

module interrupt1x8_controller (
	input BUS_CLK,
	input RESET,
	output ACK,
	input ACTV_BAR,
	input [15:0] ADDR,
	output [7:0] RD_DATA,
	input WEN,
	input [7:0] WRT_DATA,
	output ACK1,
endmodule //interrupt1x8_controller

The red colored ports are part of some processor bus and the interrupt controller is a slave to this bus. Lets call this bus SPB bus. As such there will be an SPB cable which will have a slave side connector at one end and a master side connector at the other end.

Following signals are defined in SPB bus which will be part of the SPB cable,
  • spb_active_n
  • spb_address[15:0]
  • spb_write_en
  • spb_read_data[7:0]
  • spb_write_data[7:0]
  • spb_done
On this imaginary box, we will affix an imaginary connector that can connect to SPB slave side. We like to label this connector as system_bus. Following SoCBuilder code in typed in Composer IDE will create this imaginary box with connector and label. Inside the box, the ports of the IP is now connected to the imaginary SPB connector. We have just standardized the IP's bus connection. We will have to go through the same process for all the ports to fully standardize the IP.

SoCBuilder Code

/////// spb slave connector ///////
interface slave of spb as system_bus;

/////// spb slave connector to IP port hookup ///////
map system_bus.spb_active_n to port ACTV_BAR;
map system_bus.spb_address to port ADDR;
map system_bus.spb_write_en to port WEN;
map system_bus.spb_read_data to port RD_DATA;
map system_bus.spb_write_data to port WRT_DATA;
map system_bus.spb_done to port ACK;

There might be IP ports those don't need to be presented to the environment outside the box via the connectors. They may have to be left unconnected or they may just have to be tied inside the box. Some of the connector pins may have to be tied as well. SoCBuilder language has facilities to deal with all these situations. Consider this box as a shrink wrapped box ready for delivery.

Deliver your IP in a shrink wrapped box

SoCBuilder language allows you to create this imaginary box, with an IP inside and connectors attached. Now the chip/SoC designer can have a simplified, organized and reusable view of your IP. This way the designer doesn’t need to worry about the details inside the box when he connects these reusable pieces together in a chip. It is almost like delivering the IP in a shrink wrapped box ready to be plugged in.

What if I need to design a complex IP from scratch?

The Composer IDE provides a better way to design a complex IP than writing all the Verilog code yourself. You can use the exact same top down approach like a chip design as if your IP is a mini chip.

Top down design with free form logic >>

Partition your complex IP into smaller manageable blocks. Arrange them freely with hierarchy of your choice. All the advanced capabilities Composer IDE to boost your productivity will be in your reach even for an IP design. Once the top down design is done using SoCBuilder language, you can automatically convert it to a shrink wrapped IP without any additional steps.

Whether you are an IP vendor or an in-house IP provider, your IP packaged and delivered this way to the chip or SoC integration team will make the IP part of a successful chip design with lot less effort.

Composer IDE is packed with even more capabilities to improve chip design productivity. Contact us to arrange for a demo to go over the full capability of Composer IDE.