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Smart IPs scale with chip need

Imagine you have a bus bridge in your design that has one master port and 4 slave ports. What if the design needs to be changed and now you need 6 slave ports. There are a few options.
  • Cascade two such 1x4 bridges if you don’t want to create a new bridge with 6 slave ports. This may amount to a nontrivial change in RTL.
  • Design a new 1x6 RTL bridge using the 1x4 bridge RTL as a reference design. This may amount to be a nontrivial task depending on the complexity of the bridge design.
  • Design a new parametrized 1xn bridge RTL using the 1x4 bridge RTL as a reference design. This is a better option since the new RTL will be reusable. However parametrization may be an impractical approach depending on the complexity of the bridge as well.
  • Create a script or software that uses existing RTL as a template and generates the RTL depending on number of slaves you require. Once generated, you can hook the generated IP in your chip RTL code. This option is most practical and robust approach for a complex IP.
If you are an IP vendor or in house IP provider, your organization may already have scripts that provides the last option shown above, for some IPs that are intended to be reused over many chips.

What is a smart IP?

Writing such a script has complex challenges too. This is why designers try to avoid this option unless absolutely necessary. What if we have a way to embrace this option instead of avoiding it? That is exactly what the Composer IDE brings to the table. Composer IDE introduces the concept of smart IP. Smart IP allows authoring and use of such script or software very practical and easy.

Why is it easy to use a smart IP?

Smart IPs enjoy the exact same abstraction as the regular IPs do that SoCBuilder language provides.

Design and standardize IPs for reuse >>

In the case of smart IPs, instead of standardizing the RTL code for regular IPs, you can use Composer IDE equally to allow the designer to standardize the RTL generation script. Therefore smart IPs can be used the exact same way and be hooked using protocol base connection. Depending on what protocol is connected to the IP and the number of connections, in SoCBuilder RTL for the IP can be generated on the fly with rest of the chip RTL. Now that is a pretty smart way for an IP to behave. Integrating the smart IP becomes a single step process. All you have to do is hook it up, and the rest just automatically happens.

How do we build smart IP?

If we have to generate a complex IP, you will agree that it is not trivial. But let use take a closer look. 

If we have to write script or software to generate RTL for a small and simple IP with only one Verilog module, that is probably trivial and quite straight forward. But in a complex IP, we probably will need to generate quite a few modules, not just one. Moreover, we will also have to generate RTL code for connecting these modules that are part of this complex IP. This is what brings the complexity in generating RTL in our case. 

Composer IDE takes this process back to the simplicity of generating small and simple one module RTL approach. Composer IDE comes with a library providing the RTL generator writers a myriad of function calls. These calls provide API support for the script writers to read all the protocol based connections to the IP and their properties. There are API function calls to create as many Verilog modules you need. This way, you can keep decomposing the IP to result to a collection of simple Verilog modules. It also has function call to connect these Verilog modules however you want. The library equally provides function call that will allow you to create as many hierarchical levels as you need inside the IP to ensure functional cohesion and encapsulation. 

Given all these support, you now only have to write code for generating RTL for simple functionalities. Everything else will be taken care of for you by the Composer IDE. The effort for generating RTL for complex IP has become nothing more than effort to generate multiple simple IPs. Your designers can embrace making smart IPs and enable your team to reuse the proven IPs to achieve the true nirvana of reuse for the IPs.

But we already have our script to generate the RTL

Of course you can reuse your existing scripts. Just wrap them up with a wrapper script. The wrapper script will extract the details of connections to the IP using the library provided. Using the information, now you can invoke your existing script with proper agruments and supporting data structure to get the job done.

Smart IPs open the door to many possibilities

You can provide interrupt controller IP that configures itself based on how many interrupts are connected to it. You can provide network on chip (NoC) that configures itself. If you are using many analog IPs inside your chip you can create a smart IP to wrap the analog IPs so that the smart IP will generate all the software registers to control and monitor an analog IP. Sky is the limit.

Whether you are an IP vendor or an in-house IP provider, your IP packaged and delivered this way to the chip or SoC integration team will make the IP part of a successful chip design with lot less effort.

Composer IDE is packed with even more capabilities to improve chip design productivity. Contact us to arrange for a demo to go over the full capability of Composer IDE.